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[VHDL-FPGA-Verilog] uart

Description: FPGA的串口模块，实现FPGA与PC机的串口通讯。-FPGA serial modules, FPGA implementation with the PC-Serial communication.
Platform: | Size: 472064 | Author: 王小 | Hits:

[VHDL-FPGA-Verilog] USB20

Description: USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.-USB2_V example FPGA project is a data transmitted to the PC through the USB2.0 sample machine.
Platform: | Size: 379904 | Author: 王陶 | Hits:

[VHDL-FPGA-Verilog] RS232capture

Description: This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file do it.
Platform: | Size: 39936 | Author: Joelmir J Lopes | Hits:

[VC/MFC] Chap17

Description: VC++ cy7c68013 usb上位机-VC++ cy7c68013 usb PC
Platform: | Size: 1777664 | Author: 凌世波 | Hits:

[VC/MFC] Chap14

Description: VC++ usb cy7c68013 上位机-VC++ usb cy7c68013 PC
Platform: | Size: 161792 | Author: 凌世波 | Hits:

[TCP/IP stack] stackfiles

Description: VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.-VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.
Platform: | Size: 81920 | Author: James | Hits:

[VHDL-FPGA-Verilog] my_uart_top

Description: 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and receive data. PC using the old tooth out of the serial debugging assistant
Platform: | Size: 3072 | Author: 刘虎 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 基于Xilinx Spartan3E的RS232驱动，能够实现FPGA与PC得通信-Xilinx Spartan3E based on the RS232 driver, to achieve a FPGA and PC communication
Platform: | Size: 512000 | Author: darkblue | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO
Platform: | Size: 4096 | Author: 赵云 | Hits:

[VHDL-FPGA-Verilog] senduard_50m

Description: 串口发送: 使用串口发送程序接收二进制码（9600波特率） ，用拨码开关控制发送二进制的高四位，按板上的第二个按钮，LED灯会相应的亮起，PC 会收到相应的数据-Serial port to send: Use the serial port to send a program to receive a binary code (9600 baud), with DIP switch control to send binary high-4, according to board the second button, LED lantern lights accordingly, PC will be closed to the corresponding data
Platform: | Size: 194560 | Author: panda | Hits:

[Program doc] rjwxdpt

Description: 软件无线电技术是用于卫星导航和第三代移动通信(3G) 数据处理和计算的最优解决方案。运用基于FPGA的So PC 嵌入式设计方法构造软件无线电系统,提高了对动态实时信号的处理能力。设计完成无线通信体系结构,以及ADC 模数转换,数字下变频,CPU 中央处理器,DSP 运算单元,PCI 桥以及数据控制等模块的详细组成。相对于目前常规系统,该系统在功耗和体积方面可节省30 以上,对高速数据流的处理和计算能力有显著提高,可以应用于Cellular/ PCS 基站,GPS 抗干扰接收机,相控阵接收机,频谱分析和3G无线通信等领域。-Software radio technology is used for satellite navigation and third-generation mobile communication (3G) data processing and computing the optimal solution. So PC using FPGA-based embedded design methods to create software-defined radio system to improve the dynamic real-time signal processing capabilities. Wireless communications architecture design is completed and the ADC analog-digital conversion, digital down conversion, CPU CPU, DSP computing unit, PCI bridge, and data control module, the detailed composition. Relative to the current conventional systems, the system can save power consumption and size are more than 30 of the high-speed data stream processing and computing power has significantly increased, can be applied to Cellular/PCS base stations, GPS anti-jamming receivers, phased array receivers, spectrum analysis, and 3G wireless communications and other fields.
Platform: | Size: 516096 | Author: x | Hits:

[Software Engineering] EP2C35_PCI

Description: 文章描述了FPGA的CYCLONE II系列芯片的PCI的最小系统的相关参考资料，对于初学者有很大的帮助！-Article describes the CYCLONE II family of FPGA-chip PCI-minimum system-related references, very helpful for beginners!
Platform: | Size: 408576 | Author: 张成 | Hits:

[VHDL-FPGA-Verilog] eda

Description: 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计，对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能，该系统无须外接D／A转换器及模拟比较器，结构简单，控制精度高，有广泛的应用前景。同时，控制系统中引入上位机控制功能，可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the design of DC motor PwM controller, DC motor speed control. Introduced with the Verilog HDL language programming controller PwM DC PwM generated module, serial communication module, steering adjustment module and other functions, the system is an external D/A converters and analog comparators, simple structure, high control precision, there a wide range of applications. Meanwhile, the introduction of PC control system control functions can be easily remote control the motor.
Platform: | Size: 4268032 | Author: 杨汉轩 | Hits:

[SCM] usb_wr_firmware

Description: CY7C68013固件 FPGA把数据通过usb写入pc slave 模式 使用 EP6 -USB:FPGA write data to PC by USB change from cypress example slave mode and use EP6 bulkloop.c firmware based on the firmware frameworks. Building this example requires the full version of the Keil Tools.
Platform: | Size: 165888 | Author: shenjianfei | Hits:

[VHDL-FPGA-Verilog] usb_wr_Verilog

Description: fpga ubs通讯模块 verlog语言 使用EZ-USB FX2-USB interface. use EZ-USB FX2 carry out PC communication with FPGA by USB.
Platform: | Size: 31744 | Author: shenjianfei | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:

[USB develop] usbFPGAconnect

Description: 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program
Platform: | Size: 7154688 | Author: 梁先国 | Hits:

[VHDL-FPGA-Verilog] miniuart2

Description: 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a PC for data exchange with custom electronic. It was built in the perspective to be very small, but efficient. It had to fit in a small FPGA. It is not suited to interface a modem as there is no control handshaking (CTS/RTS). It integrate two separate clocks, one for wishbone bus, the other for bitstream generation. This has the advantage to let the user bring his own desired frequency for the baudrate.
Platform: | Size: 2588672 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] code

Description: 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
Platform: | Size: 15360 | Author: DC | Hits:

[VHDL-FPGA-Verilog] SOCKET

Description: 基于de2开发板与pc机之间传输的实验，有详细的实验步骤和全面的资料，socket程序-De2-based development board and transfer between pc machine experiments, a detailed and comprehensive information on experimental procedures, socket program
Platform: | Size: 1817600 | Author: 郝蕾 | Hits:
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